Panasonic Corporation today announced that it has achieved a conversion efficiency of 25.6% (cell area*3: 143.7 cm2) in its HIT® solar cells, a major increase over the previous world record for crystalline silicon-based solar cells.
The previous record*4 for the conversion efficiency of crystalline silicon-based solar cells of a practical size (100 cm2 and over) was 24.7%, as announced by Panasonic in February 2013 (cell area: 101.8 cm2). The new record is 0.9 points higher and the first to break through the 25% barrier for practical size cells.
This new record is also an improvement of 0.6 points over the previous record for small area crystalline silicon-based solar cells (cell area: 4 cm2) of 25.0%*4, 5.
The achievement of this new record was made possible by further development of Panasonic’s proprietary heterojunction technology*6 to realize the high conversion efficiency and superior high temperature properties of the company’s HIT solar cells as well as adopting a back-contact solar cell structure, with the electrodes on the back of the solar cell, which allows the more efficient utilization of sunlight.
Outline of the core technologies behind the record conversion efficiency
1. Reduction in recombination loss
A key feature of HIT technology is its ability to reduce the recombination loss*7 of charge carriers*8, particles of electricity generated by light, through laminating layers of high-quality amorphous silicon on the surface of the monocrystalline silicon substrate, where power is generated. By utilizing the technology to form a high-quality amorphous silicon film on the monocrystalline substrate while minimizing damage to the surface of the substrate, it has been possible to realize a high temperature coefficient*9 of -0.25% per degree Celsius*10 which is able to maintain a high conversion efficiency even with high open circuit voltage (Voc)*11 and at high temperatures.
2. Reduction in optical loss
In order to increase the current in a solar cell, it is necessary to lead the sunlight which arrive at the cell's surface to the monocrystalline silicon substrate, which is the layer which generates the power with less loss. Placing the electrodes on the reverse as back contacts allows the light to reach the substrate more efficiently. This has led to a marked improvement in short circuit current density (Jsc)*12 to 41.8mA/cm2 over Panasonic's previous figure of 39.5mA/cm2 (in the case of a cell with a conversion efficiency of
3. Minimizing resistance loss
In solar cells, the generated electrical current is accumulated in the surface grid electrodes and output externally. Previously, the grid electrodes on the light-receiving side were optimized by balancing the thickness of the grid electrodes (thinning the grid electrodes to reduce the amount of light blocked) and the reduction of electrical resistance loss, but by placing the electrodes on the reverse side, it has become possible to reduce the resistive loss when the current is fed to the grid electrodes. In addition, a high fill factor (FF)*13 of 0.827, has been achieved, even at a practical cell size by improving resistance loss in the amorphous silicon layer.
Going forward, Panasonic will continue to pursue technology development of its HIT solar cells, aimed at realizing higher efficiency, lower costs and the more efficient use of resources, and will work towards mass production.
*HIT is a registered trademark of the Panasonic Group.
Open-circuit voltage (Voc)*9 0.740 V
Short circuit current (Isc)*12 6.01 A
Short circuit current density (Jsc)*12 41.8 mA/cm2
Fill factor (FF)*13 0.827
Cell conversion efficiency 25.6%
Cell area*3 143.7 cm2
*1 According to research by Panasonic as of April 10, 2014, for non-concentrating silicon solar
cells (regardless of cell area).
*2 Result of evaluations at the National Institute of Advanced Industrial Science and Technology
*3 The cell area is the area opened by the masks.
*4 Judged from the "Solar cell efficiency tables (version 43)" [Prog. Photovolt: Res. Appl. 2014; 22:1–9]
*5 University of New South Wales (Australia) (March 1999)
*6 Technology for junction formation required for solar cells that covers the silicon base surface with an amorphous silicon layer. Has the key feature of superior passivation to compensate for the many flaws around the silicon base surface area.
*7 Resistive loss is where positive and negative charges generated in the solar cell combine and are consequently lost inside the cell, lowering the current and voltage that can be output and accordingly decreasing the solar cell's output.
*8 The charge carrier is a particle of electricity containing an electron (negative) and a hole (positive). While the electron has a negative charge, the hole has a positive charge left from the disappearance of an electron.
*9 The temperature coefficient is a value expressing the ratio of conversion efficiency changes when the temperature rises by one degree.
*10 Value measured by Panasonic in assessing a similar cell. The previous HIT temperature coefficient was -0.29% per degree Celsius. The temperature coefficient of ordinary crystalline silicon solar cells is around -0.4 to -0.5% per degree Celcius. The lower the (absolute) value, the less the conversion efficiency drops under high temperatures.
*11 Open-circuit voltage (Voc) is the maximum voltage the cell can generate.
*12 The short circuit current (Isc) is the maximum current generated from a solar cell. The short circuit current density (Jsc) is the value found by dividing the Isc by the cell area.
*13 The fill factor (FF) is a value gained by dividing the maximum obtainable power of the solar cell by to the product of the open-circuit voltage and short-circuit current; the closer to 1 this is, the better the result.